An asynchronous transfer mode (ATM) network is a communication network which can transfer information from one or more sources to one or more destinations. The communication network itself may be composed of multiple communicating nodes (e.g., terminals, routers, servers, switches, etc.) that are interconnected to each other by physical communication links (wires, cables, optical fibers, RF channels, etc.). A node transmits a signal containing a bitstream to an adjacent node via the communication link that connects the two adjacent nodes. The transmitted bitstream is organized into fixed sized packet or "cell" slots for carrying 53 byte packets called cells. Each cell has a 5 byte header, for communicating control information, and a 48 byte payload for communicating a message to be conveyed between nodes. A node allocates a "virtual channel" to each communication, which amongst other things, identifies an adjacent node to which cells of the communication must be transmitted. A sequence of virtual channels of nodes on a path between a source node and a destination node identifies a virtual channel connection. The source node transmits cells to the destination node via this sequence of virtual channels, i.e., from node to node on the path, in a bucket brigade like fashion. Prior to transmitting the information, the source node segments the information into 48 byte sized messages and appends a 5 byte header to each such message to form a cell. The source node writes a virtual address into the cell header, such as a virtual channel identifier, which enables each node on the path that receives the cell to determine the outgoing virtual channel on which to transmit the cell. A destination node receiving the cells extracts the messages from the payloads and reassembles the messages (in the appropriate order) into the originally transmitted information.
Consider that cells are received at each node from a variety of communication links. It is possible that multiple cells are contemporaneously received that must be outputted on the same communication link. Because only one cell can be outputted at a time on the same communication link, the contemporaneously received cells must be transmitted sequentially. Thus, cells may be temporarily buffered pending transmission. Such buffering introduces a latency in the delivery of the cell. In the alternative, a transmitted cell may be discarded because it is received at a congested node (a node receiving far more cells than can be transmitted) or received with uncorrectable errors at the node. When a cell is discarded, it is often retransmitted from the source at a later time. The latency incurred by cells of a specific communication varies from moment to moment in the communication network. As a result, jitter is introduced into the delivery of information from the source node to the destination node.
It is desirable to support delivery of constant bit rate (CBR) services, such as audio and voice communication using an ATM network. However, CBR communications must be delivered in a synchronous, de-jittered fashion. Otherwise, the CBR communication will contain discontinuities or gaps which degrade the communication or render the communication completely unintelligible.
If the service clock signal is known, the destination node can attempt to regenerate the same service clock for resynchronizing the received CBR information. The problem is that the locally generated clock at the destination node is subject to drift and will not track the remote service clock at the source node with sufficient accuracy to enable proper resynchronization of the received CBR information.
FIG. 1 illustrates a system for overcoming these problems associated with communicating a CBR service via an ATM network disclosed in U.S. Pat. No. 5,260,978. In FIG. 1, CBR data produced in synchronism with an original service clock is segmented into packets by SAR (segmentation and reassembly) and SRTS generator circuit 14 of a source node 12. In addition, the original service clock, and a network clock, are used to generate time stamps, referred to as synchronous residual time stamps (SRTS samples), in segmentation and reassembly (SAR) and SRTS generator circuit 14 as described below. The network clock can be any clock signal available throughout the network, such as the OC3/DS3 155 Mbit/sec data link bit clock used for synchronizing the transmission of the bitstream of various links of the ATM network 16. The SRTS samples are inserted into the headers of the cells carrying the CBR data and transmitted via the ATM network 16 to the destination node 18. At the node 18, an SAR and service clock regenerator circuit 20 reassembles the CBR data stream. The SAR and service clock recovery circuit 20 furthermore extracts the SRTS samples. Using the network clock and the SRTS samples, the SAR and service clock recovery circuit regenerates the service clock and resynchronizes the received CBR data.
FIG. 2 illustrates how SRTS samples are generated. The SAR and SRTS generator 14 counts the number of network clock ticks in each successive interval 22, 24 of 3008 service clocks. Representations of these counts form the SRTS samples transmitted in cells. At the SAR and service clock regenerator circuit 20 of destination node 18, a service clock that has exactly the same frequency as the original, remote service clock at the node 12 is generated.
The SAR and service clock regenerator circuit 20 counts network clock ticks. A representation of each locally generated count of network clock ticks forms a local SRTS sample. The local SRTS sample is compared to a corresponding representation of an incoming, remote SRTS sample extracted from incoming cells. The locally generated service clock is then adjusted based on a difference between the two SRTS samples.
The locally generated counts will only vary slightly from the counts of the remote service clock. Thus, the representations of the local and remote SRTS samples include only a sequence of the least significant four bits of the counts or SRTS samples.
FIG. 3 shows a prior art service clock regenerator 30. Incoming remote SRTS samples (of the remote service clock of the source node 12) received at the destination node 18 are temporarily stored in FIFO 32. Meanwhile, a network clock, having a frequency of F.sub.NET is fed to a frequency divider 34 which produces a lower frequency network clock having a frequency F.sub.NETx =F.sub.NET /x. The value of x may be chosen in relation to the frequency of the service clock so that the lower frequency network clock is greater in frequency than the service clock but less than twice the frequency of the service clock. The reduced frequency network clock is fed to the increment input of a 4-bit free-running roll-over counter 36. Herein, a "roll-over counter" is a counter that repeatedly counts up to a maximum count, wraps around to zero after reaching the maximum count, and continues to count up to the maximum value.
Each locally generated count of the counter 36 is outputted to a 4-bit comparator 38. The 4-bit comparator 38 also receives a corresponding remote SRTS. When the local count of the counter 36 reaches a value equal to the received remote SRTS with which it is compared, a pulse is outputted. The pulses outputted from the comparator 38 are gated through AND gate 40. That is, the AND gate 40 also receives a clock signal from a gate counter 42 running at the SRTS sampling period rate, e.g., about 513 Hz for a 1.544 MHZ T1 service clock. These gated pulses are then multiplied by 3008 in an analog phase-locked loop (PLL) 44 to regenerate the service clock.
FIG. 4 shows an alternative prior art service clock regenerator 50. Like the service clock regenerator 30 of FIG. 3, incoming SRTS samples of the remote service clock at the source node are temporarily stored in an incoming SRTS sample FIFO 52. Meanwhile, the network clock with frequency F.sub.NET is fed to a frequency divider that divides the network clock signal frequency by x to produce a clock with frequency F.sub.NETx. The reduced frequency network clock signal is fed to a local SRTS generator 56. The local SRTS generator 56 also receives the recovered service clock outputted from a course tuning oscillator 60. The local SRTS generator 56 counts the number of ticks of the reduced frequency network clock modulo 16 that occur every SRTS interval (of 3008 ticks of the recovered service clock). This produces a local 4-bit SRTS sample of the locally regenerated service clock. The local SRTS sample is then compared with (i.e., subtracted from) a corresponding incoming remote SRTS sample of the remote clock in a phase comparator 58. This difference, which represents the phase difference between the local service clock and the remote service clock, is then fed to the coarse tuning oscillator 60 to adjust the frequency of the local service clock. That is, when the locally regenerated service clock leads the remote service clock (locally generated SRTS sample is greater than incoming SRTS sample), the frequency of the coarse tuning oscillator 60 is reduced. Likewise, when the locally regenerated service clock lags the remote service clock (locally generated SRTS sample is less than the incoming SRTS sample), the frequency of the coarse tuning oscillator 60 is increased.
One problem associated with the two system clock regenerators 30 and 50 is that they both use a simple difference between a parameter of the local service clock and a parameter of the remote service clock. However, this is not exactly equivalent to the phase difference between the local service clock and the remote service clock. Rather, it is merely an indication of the difference in count between the two. In other words, if the local service clock had the identical frequency as the remote service clock but the local count was different than the received SRTS, the service clock regenerators 30 and 50 would nevertheless attempt to adjust the frequency of the local service clock. In addition, in the service clock regenerators 30 and 50, the two values subtracted in the comparators 38, 58 are both generated by 4-bit roll-over counters. If one counter counts faster than the other, it is possible for the faster counter to roll-over before the other counter. If a difference is formed between the counts of these two counters at that moment, then the slower counter will have a higher count than the faster counter. Thus, the difference will have the wrong polarity thereby causing an opposite frequency adjustment as should be applied (i.e., the frequency of the local service clock will be increased when it should be decreased or vice versa). Both of these limitations tend to increase the PLL acquisition time and to destabilize the PLL tracking.
A second problem with the service clock regenerators 30 and 50 is that no filtering is applied to the adjustment signal produced by the comparison circuit 38 or 58. This is undesirable because it tends to adjust the frequency of the service clock too rapidly.
It is an object of the present invention to overcome the disadvantages of the prior art.
The service clock regenerator 30 uses an analog PLL. Such a PLL is difficult to incorporate into a digital integrated circuit. On the other hand, the PLL used in service clock regeneration includes an oscillator which must oscillate at a selectable frequency F/X, where F is a constant, but X is a selectable real number. This can be achieved in the prior art by oscillating the frequency synthesizer at a frequency F/N for a selectable number of K periods. The frequency synthesizer then oscillates at a frequency of F/(N+1) for L-K periods. This is repeated during successive L period intervals to achieve a frequency between F/N and F/(N+1). Although over L periods, the frequency synthesizer nominally produces a signal having the correct frequency, the frequency synthesizer oscillates too slowly during too many (K) consecutive periods and then oscillates too quickly during too many subsequent (L-K) consecutive periods. It is an object of the present invention to improve on this technique.
It is also an object of the present invention to provide an architecture that is modular and easily scalable, e.g., on an integrated circuit.
It is a further object of the present invention to provide a flexible service clock architecture that can selectively recover a service clock from remotely originating SRTS samples or generate SRTS samples for enabling regeneration of a local service clock at a remote node.